1. Field of the Invention
The present invention relates to nonvolatile memory devices. In particular, the present invention relates to a nonvolatile memory device having memory cells with the electric resistance varied according to the level of storage data written by a data write current.
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device is now the focus of attention as a new-generation nonvolatile memory device. The MRAM device uses a plurality of thin-film magnetic elements formed in a semiconductor integrated circuit to store data in nonvolatile manner, with each of the thin-film magnetic elements being randomly accessible.
In recent years, it has been published that memory cells of thin-film magnetic elements with magnetic tunnel junctions are used to achieve dramatic improvements in performance of the MRAM device. The MRAM device including memory cells with magnetic tunnel junctions is disclosed for example in technical papers: xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell,xe2x80x9d ISSCC Digest of Technical Papers, TA7.2, February 2000, xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elements,xe2x80x9d ISSCC Digest of Technical Papers, TA7.3, February 2000 and xe2x80x9cA 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM,xe2x80x9d ISSCC Digest of Technical Papers, TA7.6, February 2001.
FIG. 14 schematically shows a structure of a memory cell having a magnetic tunnel junction (this memory cell is hereinafter referred to as xe2x80x9cMTJ memory cellxe2x80x9d).
Referring to FIG. 14, the MTJ memory cell includes a tunneling magneto-resistance element TMR having an electric resistance varying according to the data level of magnetically written storage data and includes an access transistor ATR. The access transistor ATR is connected in series with the tunneling magneto-resistance element TMR between a bit line BL and a source voltage line SL. The access transistor ATR is typically a field-effect transistor formed on a semiconductor substrate.
To the MTJ memory cell, the bit line BL and a write digit line WDL for allowing respective data write currents to flow in different directions respectively in data writing, a word line WL for reading data, and the source voltage line SL for pulling down the tunneling magneto-resistance element TMR to a ground voltage GND in data reading are provided. In data reading, the access transistor ATR is turned on and, in response to this turn-on, the tunneling magneto-resistance element TMR is electrically coupled between the source line SL and the bit line BL.
FIG. 15 conceptually shows an operation of writing data into the MTJ memory cell.
Referring to FIG. 15, the tunneling magneto-resistance element TMR includes a ferromagnetic layer FL having a fixed direction of magnetization (hereinafter referred to as xe2x80x9cfixed magnetic layerxe2x80x9d), and a ferromagnetic layer VL magnetized in a direction according to an externally applied magnetic field (hereinafter referred to as xe2x80x9cfree magnetic layerxe2x80x9d). Between the fixed magnetic layer FL and the free magnetic layer VL, a tunneling barrier (tunneling film) TB formed of an insulating film is provided. According to the level of storage data to be written, the free magnetic layer VL is magnetized in the same direction as or in a different direction from the direction in which the fixed magnetic layer FL is magnetized. The fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL constitute a magnetic tunnel junction.
The tunneling magneto-resistance element TMR has an electric resistance varying according to a relative relation between respective directions of magnetization of the fixed magnetic layer FL and the free magnetic layer VL. Specifically, the tunneling magneto-resistance element TMR has a minimum electric resistance Rmin when the fixed magnetic layer FL has a magnetization direction which is the same as (in parallel with) that of the free magnetic layer VL and has a maximum electric resistance Rmax when respective magnetization directions of the fixed magnetic layer FL and the free magnetic layer VL are opposite to (in antiparallel with) each other.
In data writing, the word line WL is inactivated to turn off the access transistor ATR. In this state, a data write current for magnetizing the free magnetic layer VL flows through each of the bit line BL and the write digit line WDL in respective directions according to the level of data to be written.
FIG. 16 conceptually shows a relation between the data write current and the magnetization direction of the tunneling magneto-resistance element in data writing.
Referring to FIG. 16, the horizontal axis H (EA) represents a magnetic field applied in the direction of an easy axis (EA) in the free magnetic layer VL in the tunneling magneto-resistance element TMR. The vertical axis H (HA) represents a magnetic field acting in the direction of a hard axis (HA) in the free magnetic layer VL. The magnetic field H (EA) and the magnetic field H (HA) correspond respectively to two magnetic fields generated by respective currents flowing through the bit line BL and the write digit line WDL.
In the MTJ memory cell, the fixed magnetization direction of the fixed magnetic layer FL is in parallel with the easy axis of the free magnetic layer VL, and the free magnetic layer VL is magnetized in the direction which is in parallel or antiparallel with (opposite to) the fixed magnetic layer FL in the direction of the easy axis according to the level (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of the storage data. The MTJ memory cell is capable of storing 1-bit data (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) according to the two magnetization directions of the free magnetic layer VL.
The magnetization direction of the free magnetic layer VL is only rewritable when the sum of the applied magnetic fields H (EA) and H (HA) falls within the region outside the asteroid characteristic line shown in FIG. 16. In other words, if the intensity of the applied data write magnetic fields corresponds to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL is not switched.
As indicated by the asteroid characteristic line, a magnetic field in the direction of the hard axis can be applied to the free magnetic layer VL to reduce a magnetization threshold which is necessary for changing the magnetization direction along the easy axis. Suppose that operating points for data writing are designed as shown in FIG. 16. Then, for the MTJ memory cell into which data is to be written, a data write magnetic field in the direction of the easy axis is designed to have its intensity equal to HWR. More specifically, the value of a data write current flowing through the bit line BL or the write digit line WDL is designed to obtain this data write magnetic field HWR. In general, the data write magnetic field HWR is represented by the sum of a switching magnetic field HSW necessary for changing the magnetization direction and a margin xcex94H: HWR=HSW+xcex94H.
In order to rewrite storage data of the MTJ memory cell, i.e., switch the magnetization direction of the tunneling magneto-resistance element TMR, a data write current of at least a predetermined level must be flown through both of the write digit line WDL and the bit line BL. Accordingly, the free magnetic layer VL in the tunneling magneto-resistance element TMR is magnetized in the direction in parallel with or opposite to (antiparallel with) the fixed magnetic layer FL according to the direction of a data write magnetic field along the easy axis (EA). The magnetization direction once written into the tunneling magneto-resistance element TMR, i.e., storage data in the MTJ memory cell, is held in nonvolatile manner until execution of writing of new data.
FIG. 17 conceptually shows an operation of reading data from the MTJ memory cell.
Referring to FIG. 17, in the data reading operation, the access transistor ATR is turned on in response to activation of the word line WL. Then, the tunneling magneto-resistance element TMR pulled down to the ground voltage GND is electrically coupled to the bit line BL.
In this state, the bit line BL is pulled up to a predetermined voltage to allow a memory cell current Icell to flow through a current path including the bit line BL and the tunneling magneto-resistance element TMR, according to an electric resistance of the tunneling magneto-resistance element TMR, i.e., the level of storage data in the MTJ memory cell. For example, the memory cell current Icell can be compared with a predetermined reference current to read the storage data from the MTJ memory cell.
In data reading, a data read current Is flows through the tunneling magneto-resistance element TMR. The data read current Is is generally designed to be smaller than the above-discussed data write current by an order or two orders of magnitude. Therefore, there is a low possibility that storage data in the MTJ memory cell is erroneously rewritten because of the influence of the data read current Is in data reading. In other words, data can be read nondestructively.
FIG. 18 shows a structure of the MTJ memory cell formed on a semiconductor substrate.
Referring to FIG. 18, the access transistor ATR formed on the semiconductor main substrate SUB includes n-type impurity regions 310 and 320 and a gate 330. Impurity region 310 is electrically coupled to the source voltage line SL via a metal film formed in a contact hole 341.
The write digit line WDL is formed in a metal interconnect layer provided above the layer of the source voltage line SL. The tunneling magneto-resistance element TMR is electrically coupled to impurity region 320 of the access transistor ATR via a strap 350 and a metal film formed in a contact hole 340. Strap 350 formed of a conductive material is provided for electrically coupling the tunneling magneto-resistance element TMR to the access transistor ATR. The bit line BL is electrically coupled to the tunneling magneto-resistance element TMR and provided above the layer of the tunneling magneto-resistance element TMR.
The bit line BL through which the data write current and the data read current flow and the write digit line WDL through which the data write current flows are formed by using metal interconnect layers. It is unnecessary to force current to flow through the word line WL since the word line WL is provided for controlling the gate voltage of the access transistor ATR. Then, in terms of improvement in the degree of integration, the word line WL is generally formed in the same interconnect layer as gate 330 by using a polysilicon or polycide layer for example, without newly providing a separate metal interconnect layer.
The MRAM device as discussed above is capable of storing data in nonvolatile manner using MTJ memory cells integrated on the semiconductor substrate. Specifically, in each of the MTJ memory cells, the tunneling magneto-resistance element TMR has its electric resistance varied according to the magnetization direction which is rewritable by the data write magnetic field, and thus nonvolatile data storage is possible by correlating the electric resistances Rmax and Rmin of the tunneling magneto-resistance element TMR with respective levels (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of storage data.
A nonvolatile memory cell of a different type drawing attention now is OUM (Ovonic Unified Memories) cell. An overview of OUM is disclosed for example in xe2x80x9cForefront of Non-Volatile Memory/The Future in Intel""s Mind: From Flash Memory to OUM,xe2x80x9d Nikkei Microdevices, March, 2002, pp. 65-78. The OUM cell is constituted of a thin-film chalcogenide layer and a heating element. The chalcogenide is converted into amorphous or chalcogenide depending on heating pattern by the heating element through which a data write current flows. The chalcogenide layer in the amorphous state has its electric resistance different from that in the crystalline state. Accordingly, two patterns of supplying the data write current that correspond respectively to two heating patterns, with the one for converting chalcogenide into amorphous and the other for converting chalcogenide into crystal are set in advance according to the level of write data so as to allow the OUM cell to store data in nonvolatile manner.
As heretofore discussed, characteristics common to the MTJ memory cell and the OUM cell are that current is supplied for writing data into the MTJ memory cell and the OUM cell and that the electric resistance varies according to storage data.
One of chief applications of the memory device is cache memory which is required to perform fast parallel input/output of multibit data. Under the current state of the art, such a cache memory uses SRAM (Static Random Access Memory) cells having, as a basic structure, CMOS (Complementary Metal Oxide Semiconductor) structure with cross-coupled latch. The SRAM cells, however, have a problem that the area of one memory cell is large or the SRAM cells are volatile memories losing data by stopping the power supply, and thus use of the SRAM cell is not necessarily convenient.
On the over hand, EEPROM (Electrically Erasable/Programmable Read-Only Memory) and so-called flash memory that are nonvolatile memory devices and generally used now require relatively long time for writing data (programming), and thus it is difficult to apply these memories to the cache memory.
The MTJ memory cells and OUM cells are new-type nonvolatile memories as described above and desirably constitute a cache memory capable of operating at a high rate. In order to apply the MTJ cells and OUM cells to the cache memory, however, parallel reading and writing operation of multibit data in consideration of the cell characteristics are necessary.
One object of the present invention is to provide peripheral circuitry of a nonvolatile memory device having memory cells such as MTJ and OUM cells with electric resistance varying in nonvolatile manner according to the level of storage data written by a data write current, the peripheral circuitry suitable for fast parallel input/output of multibit data.
A nonvolatile memory device according to one aspect of the present invention includes a plurality of memory cell blocks that are selectively accessed, the memory cell blocks each including a plurality of memory cells arranged in a matrix and each having an electric resistance varying according to storage data written in nonvolatile manner by a data write current and a plurality of bit lines respectively provided correspondingly to memory cell columns. The nonvolatile memory device further includes a plurality of row selection circuits respectively provided correspondingly to the memory cell blocks, the row selection circuits each selecting memory cell rows in a corresponding memory cell block, and peripheral circuitry for writing and reading data of multiple bits in parallel, the data being input/output to/from a data node, into and from at least a part of memory cells in the selected memory cell row, through at least a part of the bit lines in a selected memory cell block which is one of the memory cell blocks. The peripheral circuitry transmits the data of multiple bits in the direction of the memory cells columns.
Accordingly, one chief advantage of the present invention is that, in the nonvolatile memory device, input/output data of multiple bits is efficiently transmitted by the peripheral circuitry in the direction of columns (bit lines) to/from a selected memory cell block into/from which data is written/read according to selected bit lines. The nonvolatile memory device is thus provided that is suitable for cache memory required to input/output data of multiple bits in parallel at a high rate.
A nonvolatile memory device according to another aspect of the present invention includes a plurality of memory cells arranged in a matrix and each having an electric resistance varying according to storage data written in nonvolatile manner by a data write current, an address latch circuit temporarily holding information for selecting memory cell rows and memory cell columns, a plurality of bit lines respectively provided correspondingly to the columns of the memory cells, a row selection circuit selecting a memory cell row according to the information held by the address latch circuit, and peripheral circuitry for writing and reading data of multiple bits in parallel, the data being input/output to/from a data node, into and from selected memory cells which are at least a part of memory cells in the selected memory cell row, through at least apart of the bit lines. The peripheral circuitry includes a data latch circuit temporarily holding the data of multiple bits transmitted between the selected memory cells and the data node, and dividing a data reading operation and a data writing operation each into a plurality of cycles to carry out the cycles in pipelining manner.
The above-described nonvolatile memory device has the peripheral circuitry dividing each of the data reading and writing operations into a plurality of stages and carrying out operations in respective stages in pipelining manner, and thus increase in speed of data reading/writing is achieved. The nonvolatile memory device is accordingly provided that is suitable for cache memory required to input/output data of multiple bits in parallel at a high speed.
A nonvolatile memory device according to still another aspect of the present invention includes a plurality of memory cells arranged in a matrix and each having an electric resistance varying according to storage data written in nonvolatile manner by a data write current, a row selection circuit for selecting memory cell rows, a plurality of bit lines respectively provided correspondingly to the memory cell columns, and peripheral circuitry for writing, through the bit lines, input data of L bits in one data writing operation, L being an integer of at least 2, into L memory cells selected from the memory cells. The peripheral circuitry includes a data latch circuit for temporarily holding the input data of L bits. In that one data writing operation, the peripheral circuitry writes a data unit (L/M) times, the data unit being input data of M bits written in parallel into M memory cells different from each other, carries out unit operation of (L/M) times, in each of the unit operations M bits of said input data of L bits written in parallel into M memory cells, M being a divisor of L and satisfying a relation 2xe2x89xa6Mxe2x89xa6L. The M memory cells in respective unit operations are different from each other.
In such a nonvolatile memory device, even if the input data to be written in one writing operation has a large number of bits, that one writing operation is divided into a plurality of stages each for writing a data unit, in order to reduce the number of bits written in parallel. Accordingly, increase of peak power consumption due to increase of the data write current is prevented. The nonvolatile memory device is accordingly provided that is suitable for cache memory required to input/output data of multiple bits in parallel at a high speed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.